Ciusbet CPU BenchMark: ¿Cómo funciona?

NOTA
El código no está totalmente optimizado, como es de esperar.
Cabe señalar que la instrucción INTO (INTerrupt on Overflow) puede
eliminarse de todos los ejemplos puesto que solo se encarga de controlar
posibles overflows.

Las direcciones de memoria son solo ilustrativas.
No todas las pruebas han sido diseñadas totalmente en ensamblador,
hay partes de las que se ha encargado el compilador

TEST: FLOAT II

[-]------------------------------------------------------------[-]
 AUTOR: Pablo Rodríguez Mier A.K.A Ciusbet
 + Implementado en Ciusbet CPU BenchMark

 + VALORES PASADOS COMO ARGUMENTO:

 - X=0.5             
   [EBP-C] (8 bytes)
 - Y=0.5             
   [EBP-14](8 bytes)
 - T=1.0         
   [4035F0](4 bytes)
 - S=0.499975 
   [4035E8](8 bytes)

[-]------------------------------------------------------------[-] 

1  |00401224  |> /33DB          /XOR EBX, EBX
2  |00401226  |. |85E4          |TEST ESP, ESP
3  |00401228  |> |DD45 F4       |/FLD QWORD PTR SS:[EBP-C]
4  |0040122B  |. |D9FE          ||FSIN
5  |0040122D  |. |D8C0          ||FADD ST, ST            
6  |0040122F  |. |DD45 F4       ||FLD QWORD PTR SS:[EBP-C]
7  |00401232  |. |D9FF          ||FCOS
8  |00401234  |. |DEC9          ||FMULP ST(1), ST
9  |00401236  |. |DD45 EC       ||FLD QWORD PTR SS:[EBP-14]
10 |00401239  |. |DC45 F4       ||FADD QWORD PTR SS:[EBP-C]
11 |0040123C  |. |D9FF          ||FCOS
12 |0040123E  |. |DD45 EC       ||FLD QWORD PTR SS:[EBP-14]
13 |00401241  |. |DC6D F4       ||FSUBR QWORD PTR SS:[EBP-C]
14 |00401244  |. |D9FF          ||FCOS
15 |00401246  |. |DEC1          ||FADDP ST(1), ST
16 |00401248  |. |D825 F0354000 ||FSUB DWORD PTR DS:[4035F0]
17 |0040124E  |. |DEF9          ||FDIVP ST(1), ST
18 |00401250  |. |D9E8          ||FLD1
19 |00401252  |. |D9F3          ||FPATAN
20 |00401254  |. |DC0D E8354000 ||FMUL QWORD PTR DS:[4035E8]
21 |0040125A  |. |DD5D F4       ||FSTP QWORD PTR SS:[EBP-C]
22 |0040125D  |. |DD45 EC       ||FLD QWORD PTR SS:[EBP-14]
23 |00401260  |. |D9FE          ||FSIN
24 |00401262  |. |D8C0          ||FADD ST, ST
25 |00401264  |. |DD45 EC       ||FLD QWORD PTR SS:[EBP-14]
26 |00401267  |. |D9FF          ||FCOS
27 |00401269  |. |DEC9          ||FMULP ST(1), ST
28 |0040126B  |. |DD45 EC       ||FLD QWORD PTR SS:[EBP-14]
29 |0040126E  |. |DC45 F4       ||FADD QWORD PTR SS:[EBP-C]
30 |00401271  |. |D9FF          ||FCOS
31 |00401273  |. |DD45 EC       ||FLD QWORD PTR SS:[EBP-14]
32 |00401276  |. |DC6D F4       ||FSUBR QWORD PTR SS:[EBP-C]
33 |00401279  |. |D9FF          ||FCOS
34 |0040127B  |. |DEC1          ||FADDP ST(1), ST
35 |0040127D  |. |D825 F0354000 ||FSUB DWORD PTR DS:[4035F0]
36 |00401283  |. |DEF9          ||FDIVP ST(1), ST
37 |00401285  |. |D9E8          ||FLD1
38 |00401287  |. |D9F3          ||FPATAN
39 |00401289  |. |DC0D E8354000 ||FMUL QWORD PTR DS:[4035E8]
40 |0040128F  |. |DD5D EC       ||FSTP QWORD PTR SS:[EBP-14]
41 |00401292  |. |83C3 01       ||ADD EBX, 1
42 |00401295  |. |CE            ||INTO
43 |00401296  |. |81FB 30750000 ||CMP EBX, 7530
44 |0040129C  |.^|7C 8A         |\JL SHORT 00401228
45 |0040129E  |. |83C1 01       |ADD ECX, 1
46 |004012A1  |. |CE            |INTO
47 |004012A2  |. |81F9 2C010000 |CMP ECX, 12C
48 |004012A8  |.^\0F8C 76FFFFFF \JL 00401224

Descripción de las instrucciones

A continuación pongo un breve comentario de lo que hace cada línea de código.

Linea Instrucción Descripción
1 XOR EBX, EBX EBX=0
2 TEST ESP, ESP AND (ESP,ESP) -> ZF=0 SI ESP=0
3 FLD QWORD PTR SS:[EBP-C] Carga primer valor en la pila de la FPU ST(0)=X
4 FSIN Calcula el seno, ST(0)=SIN(ST(0)) -> ST(0)=SENO(X)
5 FADD ST, ST ST(0)=ST(0)*2 -> 2*SENO(X)
6 FLD QWORD PTR SS:[EBP-C] Carga QWORD de Stack Segment[EBP-C] (X). ST(0) se pasa a ST(1). ST(0)=QWORD cargado
7 FCOS Calcula el coseno del nuevo valor, ST(0)=COS(X)
8 FMULP ST(1), ST Multiplica y POP. ST(1)=ST(1)*ST(0). Se hace POP: ST(0)=ST(1), ST(1)=VACIO
9 FLD QWORD PTR SS:[EBP-14] Carga en el top de la pila el siguiente valor (Y)
10 FADD QWORD PTR SS:[EBP-C] Suma X+Y. En ST(0) tenemos Y. FADD almacena el resultado en ST(0). En EBP-C esta X
11 FCOS Calcula el coseno de X
12 FLD QWORD PTR SS:[EBP-14] Carga Y. "Y" pasa a ST(0) y COS(X) a ST(1)
13 FSUBR QWORD PTR SS:[EBP-C] Resta (FSUBR: Invierte operadores). ST(0)=(X-Y)=0
14 FCOS Coseno(X-Y)=COS(0)=1 ->ST(0)=1
15 FADDP ST(1), ST Suma y POP. COS(X-Y)+COS(X); ST(0)=1+COS(X); POP ST(1)
16 FSUB DWORD PTR DS:[4035F0] Resta: ST(0) - T = 1+COS(X)-1 = COS(X)
17 FDIVP ST(1), ST Divide y POP. ST(1)/ST -> ST(0)=ST(1); POP ST(1)
18 FLD1 Carga constante 1. ST(1)=ST(0); ST(0)=1
19 FPATAN Calcula arcotangente parcial
20 FMUL QWORD PTR DS:[4035E8] Multiplica ST(0)*S
21 FSTP QWORD PTR SS:[EBP-C] Store And Pop: Guarda ST(0) en X, hace POP. La pila queda vacia
22 FLD QWORD PTR SS:[EBP-14] Carga Y. ST(0)=Y
23 FSIN ST(0)=SIN(Y)
24 FADD ST, ST ST(0)=SIN(Y)+SIN(Y)
25 FLD QWORD PTR SS:[EBP-14] ST(1)=ST(0), ST(0)=Y
26 FCOS ST(0)=COS(Y)
27 FMULP ST(1), ST ST(1)=ST(1)*ST(0)=(SIN(Y)+SIN(Y))*COS(Y); POP -> ST(0)=ST(1), ST(1)=VACIO
28 FLD QWORD PTR SS:[EBP-14] Carga Y, ST(1)=ST(0), ST(0)=Y
29 FADD QWORD PTR SS:[EBP-C] ST(0)=X+Y
30 FCOS ST(0)=COS(X+Y)
31 FLD QWORD PTR SS:[EBP-14] Carga Y, ST(0)=Y, ST(1)=COS(X+Y), ST(2)=(SIN(Y)+SIN(Y))*COS(Y)
32 FSUBR QWORD PTR SS:[EBP-C] FSUB=ST(0)-X; FSUBR=X-ST(0) (notar diferencia)
33 FCOS ST(0)=COS(ST(0)) = COS(X-ST(0))
34 FADDP ST(1), ST ST(0)+ST(1), POP
35 FSUB DWORD PTR DS:[4035F0] ST(0)=ST(0)-T
36 FDIVP ST(1), ST ST(0)=ST(1)/ST, POP
37 FLD1 Carga 1, ST(1)=ST(0), ST(0)=1.0
38 FPATAN ST(0)=Arcotangente parcial(ST(0))
39 FMUL QWORD PTR DS:[4035E8] ST(0)=ST(0)*S
40 FSTP QWORD PTR SS:[EBP-14] Y=ST(0)
41 ADD EBX, 1 EBX=EBX+1
42 INTO Interrupt On Overflow
43 CMP EBX, 7530 Compara EBX con 7530 (límite del bucle)
44 JL SHORT 00401228 Jump Less: Salta si el resultado de la comparación es menor que
45 ADD ECX, 1 ECX=ECX+1
46 INTO INTerrupt on Overflow
47 CMP ECX, 12C Compara ECX con 0x12C
48 JL 00401224 Salta si la comparación resulta ECX menor que 0x12C

TEST: FLOAT I

[-]------------------------------------------------------------[-]
 AUTOR: Pablo Rodríguez Mier A.K.A Ciusbet
 + Implementado en Ciusbet CPU BenchMark

 + VALORES PASADOS COMO ARGUMENTO:

    - T = 0.499975
    [4035E8]
    - X1= 1.0
    [EBP-8 ]
    - X2= -1.0
    [EBP-10]
    - X3= -1.0
    [EBP-18]
    - X4= -1.0
    [EBP-20]
[-]------------------------------------------------------------[-]

1  |00401474  |> /DD45 F0       /FLD QWORD PTR SS:[EBP-10]
2  |00401477  |. |DC45 F8       |FADD QWORD PTR SS:[EBP-8]
3  |0040147A  |. |DC45 E8       |FADD QWORD PTR SS:[EBP-18]
4  |0040147D  |. |DC65 E0       |FSUB QWORD PTR SS:[EBP-20]
5  |00401480  |. |DC0D E8354000 |FMUL QWORD PTR DS:[4035E8]
6  |00401486  |. |DD55 F8       |FST QWORD PTR SS:[EBP-8]
7  |00401489  |. |DC45 F0       |FADD QWORD PTR SS:[EBP-10]
8  |0040148C  |. |DC65 E8       |FSUB QWORD PTR SS:[EBP-18]
9  |0040148F  |. |DC45 E0       |FADD QWORD PTR SS:[EBP-20]
10 |00401492  |. |DC0D E8354000 |FMUL QWORD PTR DS:[4035E8]
11 |00401498  |. |DD55 F0       |FST QWORD PTR SS:[EBP-10]
12 |0040149B  |. |DC6D F8       |FSUBR QWORD PTR SS:[EBP-8]
13 |0040149E  |. |DC45 E8       |FADD QWORD PTR SS:[EBP-18]
14 |004014A1  |. |DC45 E0       |FADD QWORD PTR SS:[EBP-20]
15 |004014A4  |. |DC0D E8354000 |FMUL QWORD PTR DS:[4035E8]
16 |004014AA  |. |DD5D E8       |FSTP QWORD PTR SS:[EBP-18]
17 |004014AD  |. |DD45 F8       |FLD QWORD PTR SS:[EBP-8]
18 |004014B0  |. |DC6D F0       |FSUBR QWORD PTR SS:[EBP-10]
19 |004014B3  |. |DC45 E8       |FADD QWORD PTR SS:[EBP-18]
20 |004014B6  |. |DC45 E0       |FADD QWORD PTR SS:[EBP-20]
21 |004014B9  |. |DC0D E8354000 |FMUL QWORD PTR DS:[4035E8]
22 |004014BF  |. |DD5D E0       |FSTP QWORD PTR SS:[EBP-20]
23 |004014C2  |. |83C1 01       |ADD ECX, 1
24 |004014C5  |. |CE            |INTO
25 |004014C6  |> |81F9 A00F0000 |CMP ECX, 0FA0
26 |004014CC  |.^\7C A6         \JL SHORT 00401474

Descripción de las instrucciones

A continuación pongo un breve comentario de lo que hace cada línea de código.

Linea Instrucción Descripción
1 FLD QWORD PTR SS:[EBP-10] Carga -1 en ST(0)
2 FADD QWORD PTR SS:[EBP-8] Suma ST(0) + X1
3 FADD QWORD PTR SS:[EBP-18] Suma ST(0) + (-1.0)
4 FSUB QWORD PTR SS:[EBP-20] Resta ST(0) - (-1.0)
5 FMUL QWORD PTR DS:[4035E8] ST(0)=ST(0)*T
6 FST QWORD PTR SS:[EBP-8] X1=ST(0); X1=(X1 + X2 + X3 - X4)*T
7 FADD QWORD PTR SS:[EBP-10] ST(0)=ST(0)+X2
8 FSUB QWORD PTR SS:[EBP-18] ST(0)=ST(0)-X3
9 FADD QWORD PTR SS:[EBP-20] ST(0)=ST(0)+X4
10 FMUL QWORD PTR DS:[4035E8] ST(0)=ST(0)*T
11 FST QWORD PTR SS:[EBP-10] X2=ST(0); X2=(X1 + X2 - X3 + X4)*T
12 FSUBR QWORD PTR SS:[EBP-8] ST(0)=X1-X2=X1-ST(0)
13 FADD QWORD PTR SS:[EBP-18] ST(0)=ST(0)+X3
14 FADD QWORD PTR SS:[EBP-20] ST(0)=ST(0)+X4
15 FMUL QWORD PTR DS:[4035E8] ST(0)=ST(0)*T
16 FSTP QWORD PTR SS:[EBP-18] X3=ST(0); X3=(X1 - X2 + X3 + X4)*T;
17 FLD QWORD PTR SS:[EBP-8] ST(0)=X1; ST(1)=X3
18 FSUBR QWORD PTR SS:[EBP-10] ST(0)=X2-ST(0) = X2 - X1
19 FADD QWORD PTR SS:[EBP-18] ST(0)=ST(0)+X3;
20 FADD QWORD PTR SS:[EBP-20] ST(0)=ST(0)+X4;
21 FMUL QWORD PTR DS:[4035E8] ST(0)=ST(0)*T
22 FSTP QWORD PTR SS:[EBP-20] X4=ST(0) Y POP; X4=(-X1 + X2 + X3 + X4)*T
23 ADD ECX, 1 ECX=ECX+1
24 INTO Interrupt On Overflow
25 CMP ECX, 0FA0 Compara ECX con 0FA0
26 JL SHORT 00401474 Salta si la comparacion resulta ECX<0xFA0
page_revision: 49, last_edited: 1174736757|%e %b %Y, %H:%M %Z (%O ago)
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